Baby steps.. could use some help...

[Heath]

I've recently started trying to read schematics and transfer them to vero for building.  It's deceptively difficult, at least for me, so I'm trying to start small.  This is my second attempt at a vero layout done from a schematic (the first was the very simple but wonderful sounding Chime Amp) so bear with me as I learn.

At the moment, I have most of my building stuff boxed up so I'm not really in a position to build anything right now, but I wanted to make a vero layout of a pedal I once built on perf board that sounded very sweet to me.  Joe Gore hosts the tonefiend.com site and this is one of his projects.

This is the Codpiece.  It is a buffer and a clean boost and it sounds wonderful.  Can someone who knows this stuff far better than me give this a glance and let me know if I'm misunderstanding how/why it works the way it does?  I would be very grateful.

Here is the schematic I worked from:





and here is the vero layout I attempted:

[rocket88]

I hear ya Heath. I just made my first layout from a schematic and posted it in the contributions forum. I already changed the board around due to a major mistake, so right now I have my fingers crossed that I got it right this time. Not sure why it seems so hard to visualize going from schematic to vero.

[IvIark]

The notes you put on the schematic are correct.  Personally I wouldn't use D1 at all because if you put in the wrong polarity supply it will blow up and take some of the board with it.  But some people do include parallel protection diodes for some reason.

The first JFET is the booster with gain variable via POT1, the second is the buffer.  You can tell this at a glance because a buffer will have the output capacitor connected to source (source follower) and the booster will have the output capacitor connected to drain (common source).

[Alex]

Hi Heath!
You've inverted Source and Gate in the transistors (easy mistake to make when reading schematics).
Check this out:
http://forum.musikding.de/cpg/albums/userpics/17486/normal_fet-pinouts.jpg

[Heath]

Thanks, guys.  I've revised it, made it a little more compact.  I've checked it against the schematic to make sure my rearrangements didn't break it... but I'm still not very good at reading schematics, so take that with a grain of salt.

D1 removed and the JFETS have been re-positioned somewhat due to me having the pinouts wrong initially.  1 more link and 1 more cut added.

[IvIark]

You've got input to drain, source to trimmer and gate grounded.  In that configuration with the flatside to the right the order is

D
S
G

[Heath]

Dammit.. how'd I do that? :p

I'm learning at least, heh.  Nothing like repetition to beat the brain into submission.

Reshuffling layout.