I had a look at the schematics and the two vero layouts (here and on the main page). There appear to be two (maybe three) problems with the layouts:
(1) There should be a 1meg resistor between the gate of Q3 and ground (the lower one) on the mu amp. The JFET won't be biased correctly without it.
(2) Likewise, the output JFET buffer should have a resistor between the gate and ground. See Jack Orman's article on "Basic Buffers" at his AMZ site.
I'm not surprised the circuit is acting odd without those resistors!
(3) To protect the MOSFET, you should probably put a 9.1V zener diode between the source and gate legs (anode at source, cathode at gate). This is optional, but it's always good to be safe with those MOSFETs.
You'll have to be creative to put the 1meg resistors into the existing layouts, or someone can redo the veros to add them in (you can add an extra column or two to John's vero).
Let me know if this fixes the problem. Thanks!